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ISL59530
Data Sheet June 12, 2006 FN6220.1
16x16 Video Crosspoint
The ISL59530 is a 300MHz 16x16 Video Crosspoint Switch. Each input has an integrated DC-restore clamp and an input buffer. Each output has a fast On-Screen Display (OSD) switch (for inserting graphics or other video) and an output buffer. The switch is non-blocking, so any combination of inputs to outputs can be chosen, including one channel driving multiple outputs. The Broadcast Mode directs one input to all 16 outputs. The output buffers can be individually controlled through the SPI interface, the gain can be programmed to x1 or x2, and each output can be placed into a high impedance mode. The ISL59530 offers a typical -3dB signal bandwidth of 300MHz. Differential gain of 0.025% and differential phase of 0.05, along with 0.1dB flatness out to 50MHz, make the ISL59530 suitable for many video applications. The switch matrix configuration and output buffer gain are programmed through an SPI/QSPITM-compatible three-wire serial interface. The ISL59530 interface is designed to facilitate both fast updates and initialization. On power-up, all outputs are high impedance to avoid output conflicts. The ISL59530 is available in a 356 ball BGA package and specified over an extended -40C to +85C temperature range. The single-supply ISL59530 can accommodate input signals from 0V to 3.5V and output voltages from 0V to 3.8V. Each input includes a clamp circuit that restores the input level to an externally applied reference in AC-coupled applications. The ISL59531 is a fully differential input version of this device.
Features
* 16x16 non-blocking switch with buffered inputs and outputs * 300MHz typical bandwidth * 0.025%/0.05 dG/dP * Output gain switchable x1 or x2 for each channel * Individual outputs can be put in a high impedance state * -90dB Isolation at 6MHz * SPI digital interface * Single +5V supply operation * Pb-free plus anneal available (RoHS compliant)
Applications
* Security camera switching * RGB routing * HDTV routing
Ordering Information
PART NUMBER ISL59530IKZ (Note) TAPE & REEL PACKAGE PKG. DWG. #
356 Ld PBGA (Pb-free) V356.27x27
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
VS+ VOVERn OVERn
16 OVERLAY INPUT 16 LOGIC CONTROL
VREF
+
2uA
Power-on
16 INPUTS
Clamp Enable
SWITCH MATRIX
16 OUTPUTS
+
2uA
Av x1, x2
Output Enable
Power-on
SDI SCLK SLATCH
SPI INTERFACE, REGISTER
SDO
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59530 Pinout
ISL59530 (356 LD BGA) TOP VIEW
A
In12 In13 In14 In15 Over15 Over14 Out13 Out12
B
Out15 Out14 Over13 Over12
C
Vover15 Vover14 Vover13 Vover12
D
In11
VSDO
Vs Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs Vs
Vover11 Out11
Over11
E F
In10
Vs
SDO
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs
Vover10 Out10 Over10
G
Vs Vs Vs Vs Vs Vs Vs
H
In9 RESET Vover9 Over9 Out9
J
SLATCH
K
In8 SCLK Vover8 Over8 Out8
L
SDI
M
In7 VREF Vover7 Out7 Over7
N P
In6
Vs Vs
Vover6
Out6
Over6
R T
In5
Vs Vs Vs
NC
Vover5
Over5
Out5
U
Vs
NC
Vs
Vs
Vs
NC
Vs
Vover0
Vs
Vs
Vover1
Vs
Vs
Vover2
Vs
Vs
Vover3
Vs
Vover4 Over4 Out4
V
In4
W
Over0 Over1 Out2 Out3
Y
In3 In2 In1 In0 Out0 Out1 Over2 Over3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
= NO BALLS Balls labelled "NC" should be left unconnected - do not tie them to ground! Balls with no labels may be tied to ground to slightly reduce thermal impedance.
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FN6220.1 June 12, 2006
ISL59530
Absolute Maximum Ratings (TA = +25C)
Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . . 6.0V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 40mA Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Maximum power supply (VS) slew rate . . . . . . . . . . . . . . . . . . 1V/s ESD Classification Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER VS VSDO AV
VS = 5V, RL = 150 unless otherwise noted. CONDITION MIN 4.5 Establishes serial data output high level AV = 1 AV = 2 1.2 0.98 1.96 -1.5 -1.5 0 0.1 -10 0.5 -20 -70 60 24 50 275 135 1.2 -5 2 8 -10 108 31 70 320 165 1.8 360 195 2.4 1 2 TYP MAX 5.5 5.5 1.02 2.04 +1.5 +1.5 3.5 3.8 1 10 35 40 UNIT V V V/V V/V % % V V A A mV mV mA mA dB mA mA mA
DESCRIPTION Power Supply Voltage Power Supply for SDO output pin Gain
GM
Gain Matching (to average of all other outputs) Video Input Voltage Range Video Output Voltage Range Input Bias Current
AV = 1 AV = 2 AV = 1 AV = 2 Clamp function disabled (DC coupled inputs) Clamp function enabled, VIN = VREF + 0.5V
VIN VOUT IB
VOS
Output Offset Voltage
AV = 1 AV = 2
IOUT
Output Current
Sourcing, RL = 10 to GND Sinking, RL = 10 to 2.5V
PSRR IS
Power Supply Rejection Ratio Supply Current
AV = 1 and AV = 2 Enabled, all outputs enabled, no load current Enabled, all outputs disabled, no load current Disabled
AC Electrical Specifications
PARAMETER BW -3dB BW 0.1dB SR TS Glitch Tover dG dP Xt VN 3dB Bandwidth 0.1dB Bandwidth Slew Rate Settling Time to 0.1%
VS = 5V, RL = 150 unless otherwise noted. CONDITION VOUT = 200mVP-P, AV = 2 VOUT = 200mVP-P, AV = 2 VOUT = 2VP-P, AV = 2 VOUT = 2VP-P, AV = 2 AV = 1 From OVER rising edge to output transition AV = 2, RL = 150 AV = 2, RL = 150 6MHz 300 MIN TYP 300 50 520 12 40 6 0.025 0.05 -85 18 740 MAX UNIT MHz MHz V/s ns mV ns %
DESCRIPTION
Switching Glitch, Peak Overlay Delay Time Diff Gain Diff Phase Hostile Crosstalk Input Referred Noise Voltage
dB nV/Hz
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FN6220.1 June 12, 2006
ISL59530 Pin Descriptions
NAME IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OVER0 OVER1 OVER2 OVER3 OVER4 OVER5 NUMBER Y8 Y6 Y4 Y2 V1 T1 P1 M1 K1 H1 F1 D1 A1 A3 A5 A7 Y10 Y12 W14 W16 V20 T20 P19 M19 K20 H20 F19 D19 A17 A15 B13 B11 W10 W12 Y14 Y16 V19 T19 DESCRIPTION Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) SLATCH J3
Pin Descriptions (Continued)
NAME OVER6 OVER7 OVER8 OVER9 OVER10 OVER11 OVER12 OVER13 OVER14 OVER15 VOVER0 VOVER1 VOVER2 VOVER3 VOVER4 VOVER5 VOVER6 VOVER7 VOVER8 VOVER9 VOVER10 VOVER11 VOVER12 VOVER13 VOVER14 VOVER15 VREF NUMBER P20 M20 K19 H19 F20 D20 B17 B15 A13 A11 V10 V12 V14 V16 V18 T18 P18 M18 K18 H18 F18 D18 C17 C15 C13 C11 M3 DESCRIPTION Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input DC-restore clamp reference input. In an AC-coupled configuration (DC-Restore clamp enabled), the sync tip of composite video inputs will be restored to this level. Set to 0.3 to 0.7V for optimum performance. In an DC-coupled configuration (DC-Restore clamp disabled), this pin should be tied to ground. Never let the VREF pin float! A floating VREF pin drifts high (and if the clamp function is enabled) will cause all of the outputs to simultaneously try to drive ~4V DC into their 150 loads. Serial Latch. Serial data is latched into ISL59530 on rising edge of SLATCH.
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FN6220.1 June 12, 2006
ISL59530 Pin Descriptions (Continued)
NAME SCLK SDI SDO NUMBER K3 L3 G3 DESCRIPTION Serial data clock Serial data input Serial data output. Can be tied to SDI of another ISL59530 to enable daisychaining of multiple devices. RESET H3 Reset input. Pull high then low to reset device, but not needed in normal operation. Tie to ground in final application. Power supply for SDO pin. Tie to +5V for a 0 to 5V SDO output signal swing. VS GND NC +5V power supply Ground No Connect - Do not electrically connect to anything, including ground.
VSDO
D3
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FN6220.1 June 12, 2006
ISL59530 Typical Performance Curves
Vs=+5V AV = 1 RL = 100 INPUT_CH 0 OUTPUT_CH 0
15pF
10pF
VS=+5V AV = 2 RL = 100 INPUT_CH 0 OUTPUT_CH 0
15pF
10pF
4.7pF
4.7pF
0pF
0pF
FIGURE 1. FREQUENCY RESPONSE - VARIOUS CL, AV = 1, MUX MODE
FIGURE 2. FREQUENCY RESPONSE - VARIOUS CL, AV = 2, MUX MODE
VS=+5V AV = 1 CL = 0pF INPUT_CH 0 OUTPUT_CH 0
150
50
VS=+5V AV = 2 CL = 0 INPUT_CH 0 OUTPUT_CH 0
150
50
500 500 1.03k 1.03k
FIGURE 3. FREQUENCY RESPONSE - VARIOUS RL, AV = 1, MUX MODE
FIGURE 4. FREQUENCY RESPONSE - VARIOUS RL, AV = 2, MUX MODE
Overlay mode AV = 1 RL = 100 CL=0pF INPUT_CH 0 OUTPUT_CH 15
Overlay mode AV = 2 RL = 100 CL=0pF INPUT_CH 0 OUTPUT_CH 15
FIGURE 5. FREQUENCY RESPONSE - OVERLAY INPUT, AV = 1
FIGURE 6. FREQUENCY RESPONSE - OVERLAY INPUT, AV = 2
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FN6220.1 June 12, 2006
ISL59530 Typical Performance Curves (Continued)
15pF 10pF
VS=+5V AV = 2 RL = 100 INPUT_CH 0 OUTPUT_CH 0
15pF 10pF
4.7pF VS=+5V AV = 1 RL = 100 INPUT_CH 0 OUTPUT_CH 0 4.7pF 0pF 0pF
FIGURE 7. FREQUENCY RESPONSE - VARIOUS CL, AV = 1, BROADCAST MODE
FIGURE 8. FREQUENCY RESPONSE - VARIOUS CL, AV = 2, BROADCAST MODE
VS=+5V AV = 1 CL = 0pF INPUT_CH 0 OUTPUT_CH 0
150
50
VS=+5V AV = 2 CL = 0pF INPUT_CH 0 OUTPUT_CH 0
50 150
503
503 1.03k
1.03k
FIGURE 9A. FREQUENCY RESPONSE - VARIOUS RL, AV = 1, BROADCAST MODE
FIGURE 10. FREQUENCY RESPONSE - VARIOUS RL, AV = 2, BROADCAST MODE
AV = 1 RL = 100 CL = 0
ADJACENT INPUT_CH14 OUTPUT_CH15
AV = 2 RL = 100 CL = 0
ADJACENT INPUT_CH14 OUTPUT_CH15
ALL HOSTILE INPUT_CH0 OUTPUT_CH15
ALL HOSTILE INPUT_CH0 OUTPUT_CH15
FIGURE 11. CROSSTALK - AV = 1
FIGURE 12. CROSSTALK - AV = 2
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FN6220.1 June 12, 2006
ISL59530 Typical Performance Curves (Continued)
THD
VS=+5V AV=2 RL=100 INPUT_CH 1 OUTPUT_CH1 FIN= 1MHz
THD
2nd HD 2nd HD VS=+5V AV=2 RL=100 INPUT_CH 1 OUTPUT_CH 1 VOP-P =2V
3rd HD
3rd HD
FIGURE 13. HARMONIC DISTORTION vs FREQUENCY
FIGURE 14. HARMONIC DISTORTION vs VOUT_P-P
FIGURE 15. DISABLED OUTPUT IMPEDANCE
FIGURE 16. ENABLED OUTPUT IMPEDANCE
MUX MODE AV = 1 RL = 100 INPUT_CH 0 OUTPUT_CH 0 RISE TIME 2.42ns MUX MODE AV = 1 RL = 100 INPUT_CH 0 OUTPUT_CH 0 FALL TIME 2.44ns
TIME (ns)
TIME (ns)
FIGURE 17. RISE TIME - AV = 1
FIGURE 18. FALL TIME - AV = 1
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FN6220.1 June 12, 2006
ISL59530 Typical Performance Curves (Continued)
MUX MODE AV = 2 RL = 100 INPUT_CH 0 OUTPUT_CH 0
FALL TIME 2.40ns RISE TIME 2.32ns MUX MODE AV = 2 RL = 100 INPUT_CH 0 OUTPUT_CH 0
TIME (ns)
TIME (ns)
FIGURE 19. RISE TIME - AV = 2
FIGURE 20. FALL TIME - AV = 2
MUX MODE AV = 1 RL=100 INPUT_CH 0 OUTPUT_CH 0 SLEW RATE 405V/s
SLEW RATE -395V/s
MUX MODE AV = 1 RL=100 INPUT_CH 0 OUTPUT_CH 0
TIME (ns)
TIME (ns)
FIGURE 21. RISING SLEW RATE - AV = 1
FIGURE 22. FALLING SLEW RATE - AV = 1
MUX MODE AV = 2 RL=100 INPUT_CH 0 OUTPUT_CH 0
SLEW RATE -420V/s SLEW RATE 430V/s MUX MODE AV = 2 RL=100 INPUT_CH 0 OUTPUT_CH 0
TIME (ns)
TIME (ns)
FIGURE 23. RISING SLEW RATE - AV = 2
FIGURE 24. FALLING SLEW RATE - AV = 2
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FN6220.1 June 12, 2006
ISL59530 Typical Performance Curves (Continued)
OUTPUT
OUTPUT
OVERLAY LOGIC INPUT
OVERLAY LOGIC INPUT
FIGURE 25. OVERLAY SWITCH TURN-ON DELAY TIME
FIGURE 26. OVERLAY SWITCH TURN-OFF DELAY TIME
AV = 2 RL = 100 INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV
AV = 2 RL = 100 INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV
FIGURE 27. DIFFERENTIAL GAIN, AV = 2
FIGURE 28. DIFFERENTIAL PHASE, AV = 2
AV = 2 RL = 100 INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV
AV = 2 RL = 100 INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV
FIGURE 29. DIFFERENTIAL GAIN, AV = 2
FIGURE 30. DIFFERENTIAL PHASE, AV = 2
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FN6220.1 June 12, 2006
ISL59530 Typical Performance Curves (Continued)
AV = 1 RL = 100 INPUT_CH 1 OUTPUT_CH1 OSC = 40mV
AV = 1 RL = 100 INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV
FIGURE 31. DIFFERENTIAL GAIN, AV = 1
FIGURE 32. DIFFERENTIAL PHASE, AV = 1
AV = 1 RL = 100 INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV
AV = 1 RL = 100 INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV
FIGURE 33. DIFFERENTIAL GAIN, AV = 1
FIGURE 34. DIFFERENTIAL GAIN, AV = 1
AV = 2 RL = 100 INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV
AV = 2 RL = 100 INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV
FIGURE 35. DIFFERENTIAL GAIN, AV = 2
FIGURE 36. DIFFERENTIAL PHASE, AV = 2
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FN6220.1 June 12, 2006
ISL59530 Typical Performance Curves (Continued)
AV = 2 RL = 100 INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV
AV = 2 RL = 100 INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV
FIGURE 37. DIFFERENTIAL GAIN, AV = 2
FIGURE 38. DIFFERENTIAL PHASE, AV = 2
AV = 1 RL = 100 INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV
AV = 1 RL = 100 INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV
FIGURE 39. DIFFERENTIAL GAIN, AV = 1
FIGURE 40. DIFFERENTIAL PHASE, AV = 1
AV = 1 RL = 100 INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV
AV = 1 RL = 100 INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV
FIGURE 41. DIFFERENTIAL GAIN, AV = 1
FIGURE 42. DIFFERENTIAL PHASE, AV = 1
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FN6220.1 June 12, 2006
ISL59530 Typical Performance Curves (Continued)
AV = 2 RL = 100 INPUT_CH 01 OUTPUT_CH 01 OSC = 40mV
AV = 2 RL = 100 INPUT_CH 01 OUTPUT_CH 01 OSC = 40mV
FIGURE 43. DIFFERENTIAL GAIN, OVERLAY, AV = 2
FIGURE 44. DIFFERENTIAL PHASE, OVERLAY, AV = 2
AV = 1 RL = 100 INPUT_CH 01 OUTPUT_CH 01 OSC = 40mV
AV = 1 RL = 100 INPUT_CH 01 OUTPUT_CH 01 OSC = 40mV
FIGURE 45. DIFFERENTIAL GAIN, OVERLAY, AV = 1
FIGURE 46. DIFFERENTIAL PHASE, OVERLAY, AV = 1
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FN6220.1 June 12, 2006
ISL59530
3dB Bandwidth, MUX Mode, AV = 1, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 5 OUTPUT CHANNELS 6 7 8 9 10 11 12 13 14 15 255 244 257 264 255 253 247 253 255 241 235 223 220 211 199 193 212 217 207 202 185 216 186 214 209 207 236 227 236 235 240 218 239 223 223 228 236 1 229 217 235 217 220 218 226 230 231 210 2 229 3 210 4 222 5 221 6 224 7 190 180 186 183 174 176 171 174 175 169 168 164 161 160 160 222 8 169 168 171 175 177 177 178 184 187 188 186 188 192 192 194 197 177 225 217 198 223 157 163 168 165 230 225 205 224 197 197 240 241 223 242 219 222 217 235 211 213 237 202 219 204 9 152 10 233 11 190 12 212 13 189 14 207 193 15 166 160 169 171 167 173 170 178 183 182 185 186 185 189 193 238
3dB Bandwidth, MUX Mode, AV = 2, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 5 OUTPUT CHANNELS 6 7 8 9 10 11 12 13 14 15 295 268 277 279 269 263 259 263 262 253 253 246 241 236 233 227 279 274 244 396 367 407 230 272 412 385 417 411 407 307 308 402 402 387 383 412 412 1 316 290 300 408 391 407 404 398 394 388 2 290 3 397 4 384 5 405 6 395 7 220 211 216 213 201 201 196 201 203 194 194 187 184 182 178 183 8 288 183 192 196 192 196 196 205 212 210 215 213 216 220 220 223 324 276 400 379 413 283 407 411 410 293 412 391 419 396 385 307 300 402 403 387 385 413 415 398 394 298 402 392 289 9 240 10 299 11 250 12 385 13 234 14 396 291 15 188 183 196 196 192 200 200 211 216 214 216 217 225 225 230 293
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FN6220.1 June 12, 2006
ISL59530
3dB Bandwidth, Broadcast Mode, AV = 1, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 5 OUTPUT CHANNELS 6 7 8 9 10 11 12 13 14 15 215 214 210 212 206 203 201 204 204 202 196 194 193 191 189 187 172 173 167 157 155 161 149 170 162 161 170 187 187 182 183 170 172 170 171 175 176 1 198 195 188 178 174 177 156 160 161 157 2 195 3 183 4 184 5 188 6 172 7 178 174 171 171 169 165 163 167 167 164 160 157 156 151 151 153 8 151 152 153 157 157 159 159 167 171 170 169 171 171 174 175 178 167 179 167 160 166 151 156 160 160 169 160 156 164 162 164 168 172 157 160 151 155 158 161 154 159 161 150 143 147 9 145 10 157 11 145 12 140 13 146 14 144 144 15 158 158 159 164 164 164 164 170 175 174 178 174 178 178 178 181
3dB Bandwidth, Broadcast Mode, AV = 2, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 5 OUTPUT CHANNELS 6 7 8 9 10 11 12 13 14 15 234 232 228 229 223 219 217 220 220 218 220 212 211 209 208 205 191 191 184 172 171 176 160 187 179 179 185 204 205 198 199 189 190 190 191 192 193 1 216 215 204 196 193 192 174 175 177 174 2 209 3 199 4 204 5 205 6 190 7 196 193 189 191 186 183 181 183 184 181 176 174 174 170 167 166 8 169 169 171 175 177 177 178 184 187 188 186 188 192 192 194 197 185 195 184 179 185 167 173 178 178 187 177 176 181 181 182 184 188 174 178 169 173 174 178 172 178 177 168 163 164 9 160 10 172 11 162 12 158 13 163 14 161 161 15 178 178 178 182 183 183 183 189 193 193 192 192 195 195 196 198
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FN6220.1 June 12, 2006
ISL59530 Block Diagram
VS+ VOVERn OVERn
16 OVERLAY INPUT 16 LOGIC CONTROL
VREF
+
2uA
Power-on
16 INPUTS
Clamp Enable
SWITCH MATRIX
16 OUTPUTS
+
2uA
Av x1, x2
Output Enable
Power-on
SDI SCLK SLATCH
SPI INTERFACE, REGISTER
SDO
General Description
The ISL59530 is a 16x16 integrated video crosspoint switch matrix with input and output buffers and On-Screen Display (OSD) insertion. This device operates from a single +5V supply. Any output can be generated from any of the 16 input video signal sources, and each output can have OSD information inserted through a dedicated, fast 2:1 mux located before the output buffer. There is also a Broadcast mode allowing any one input to be broadcast to all 16 outputs. A DC restore clamp function enables the ISL59530 to AC-couple incoming video. The ISL59530 offers a -3dB signal bandwidth of 300MHz. Differential gain and differential phase of 0.025% and 0.05 respectively, along with 0.1dB flatness out to 50MHz make this ideal for multiplexing composite NTSC and PAL signals. The switch matrix configuration and output buffer gain are programmed through an SPI/QSPITM-compatible, three-wire serial interface. The ISL59530 interface is designed to facilitate both fast initialization and configuration changes. On power-up, all outputs are initialized to the disabled state to avoid output conflicts in the user's system.
daisy-chaining of multiple devices. The serial clock can run at up to 5MHz (5Mbits/s).
Serial Interface
The ISL59530 is programmed through a simple serial interface. Data on the SDI (serial data input) pin is shifted into a 16-bit shift register on the rising edge of the SCLK (serial clock) signal. (This is continuously done regardless of the state of the SLATCH signal.) The LSB (bit 0) is loaded first and the MSB (bit 15) is loaded last (see the Serial Timing Diagram). After all 16 bits of data have been loaded into the shift register, the rising edge of SLATCH updates the internal registers. While the ISL59530 has an SDO (Serial Data Out) pin, it does not have a register readback feature. The data on the SDO pin is an exact replica of the incoming data on the SDI pin, delayed by 15.5 SCLKs (an input bit is latched on the rising edge of SLCK, and is output on SDO on the falling edge of SLCK 15.5 SCLKs later). Multiple ISL59530's can be daisy-chained by connecting the SDO of one to the SDI of the other, with SCLK and SLATCH common to all the daisychained parts. After all the serial data is transmitted (16 bits * n devices = 16*n SCLKs), the rising edge of SLATCH will update the configuration registers of all n devices simultaneously. The Serial Timing Diagram and Serial Timing Parameters table show the timing requirements for the serial interface.
Digital Interface
The ISL59530 uses a serial interface to program the configuration registers. The serial interface uses three signals (SCLK, SDI, and SLATCH) for programming the ISL59530, while a fourth signal (SDO) enables optional
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FN6220.1 June 12, 2006
ISL59530 Serial Timing Diagram
SLATCH
SLATCH falling edge timing/placement is a "don't care." Serial data is latched only on rising edge of SLATCH. tSL
T
SCLK
tSD
tHD
tw
SDI
B0 (LSB) B0
(previous)
B1
B2
B15 (MSB) B15
(previous)
SDO
B1
(previous)
B2
(previous)
B0 (LSB)
B1
B2
SDO = SDI delayed by 15.5 SCLKs to allow daisy-chaining of multiple ISL59530s. SDO changes on the falling edge of SCLK.
TABLE 1. SERIAL TIMING PARAMETERS PARAMETER T tW tSD tHD tSL RECOMMENDED OPERATING RANGE 200ns 0.50 * T 20ns 20ns 20ns SCLK period Clock Pulse Width Data Setup Time Data Hold Time Final SLCK rising edge (latching B15) to SLATCH rising edge DESCRIPTION
Programming Model
The ISL59530 is configured by a series of 16 bit serial control words. The three MSBs (B15-13) of each serial word determine the basic command:
TABLE 2. COMMAND FORMAT B15 0 0 0 0 1 B14 0 0 1 1 1 B13 0 1 0 1 1 COMMAND INPUT/OUTPUT: Maps input channels to output channels OUTPUT ENABLE: Output enable for individual channels GAIN SET: Gain (x1 or x2) for each channel BROADCAST: Enables broadcast mode and selects the input channel to be broadcast to all output channels CONTROL: Clamp on/off, operational/standby mode, and global output enable/disable NUMBER OF WRITES 16 (1 channel per write) 4 (4 channels per write) 4 (4 channels per write) 1 1
Mapping Inputs to Outputs Inputs are mapped to their desired outputs using the input/output control word. Its format is:
TABLE 3. INPUT/OUTPUT WORD B15 0 B14 0 B13 0 B12 I3 B11 I2 B10 I1 B9 I0 B8 0 B7 0 B6 0 B5 0 B4 O3 B3 O2 B2 O1 B1 O0 B0 0
I3:I0 form the 4 bit word indicating the input channel (0 to 15), and O3:O0 determine the output channel which that input channel will map to. One input can be mapped to one or multiple outputs. To fully program the ISL59530, 16 INPUT/OUTPUT words must be transmitted - one for each input channel.
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Enabling Outputs The output enable control word is used to enable individual outputs. There are 16 channels to configure, so this is accomplished by writing 4 serial words, each controlling a bank of four outputs at a time. The bank is selected by bits B9 and B8. The output enable control word format is:
TABLE 4. OUTPUT ENABLE FORMAT B15 B14 B13 B12 B11 B10 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 B9 0 0 1 1 B8 0 1 0 1 B7 B6 O3 O7 O11 O15 B5 B4 O2 O6 O10 O14 B3 B2 O1 O5 O9 O13 B1 B0 O0 O4 O8 O12
Setting the ON bit = 0 tristates the output. Setting the ON bit = 1 enables the output if the Global Output Enable bit is also set (the individual output enable bits are ANDed with the Global Output Enable bit before they are sent to the output stage). Setting the Gain The gain of each output may be set to x1 or x2 using the Gain Set word. It is in the same format as the output enable control word:
TABLE 5. GAIN SET FORMAT B15 B14 B13 B12 B11 B10 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B9 0 0 1 1 B8 0 1 0 1 B7 B6 G3 G7 G11 G15 B5 B4 G2 G6 G10 G14 B3 B2 G1 G5 G9 G13 B1 B0 G0 G4 G8 G12
Set GN = 0 for a gain of x1 or 1 for a gain of x2. Broadcast Mode The Broadcast Mode routes one input to all 16 outputs. The broadcast control word is:
TABLE 6. BROADCAST FORMAT B15 0 B14 1 B13 1 B12 I3 B11 I2 B10 I1 B9 I0 B8 0 B7 0 B6 0 B5 0 B4 0 B3 0 B2 0 B1 0 B0 Enable Broadcast 0: Broadcast Mode Disabled 1: Broadcast Mode Enabled
I3:I0 form the 4 bit word indicating the input channel (0 to 15) to be sent to all 16 outputs. Set the Enable Broadcast bit (B0) = 1 to enable Broadcast Mode, or to 0 to disable Broadcast Mode. When Broadcast Mode is disabled, the previous channel assignments are restored. Control Word The ISL59530's power-on reset disables all outputs and places the part in a low-power standby mode. To enable the device, the following control word should be sent:
TABLE 7. CONTROL WORD FORMAT B15 B14 B13 B12 B11 B10 1 1 1 0 0 0 B9 B8 B7 B6 B5 B4 B3 B2 0 0 0 0 0 0 B1 B0
0 Clamp 0: Clamp Disabled 1: Clamp Enabled
Global Output Enable Power 0: All outputs tristated 0: Standby 1: Operational 1: Individual Output Enable bits control outputs
The Clamp bit enables the input clamp function, forcing the AC-coupled signal's most negative point to be equal to VREF. Note: The Clamp bit turns the DC-Restore clamp function on or off for all channels - there is no DC-Restore on/off control for individual channels. The DC-Restore function only works with signals with sync tips (composite video). Signals that do not have sync tips (the Chroma/C signal in s-video and the Pb, Pr signals in Component video), will be severely distorted if run through a DC-Restore/clamp function. 18
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For this reason, the ISL59530 must be in DC-coupled mode (Clamp Disabled) to be compatible with s-video and component video signals.
Linear Operating Region
In addition to bandwidth optimization, to get the best linearity the ISL59530 should be configured to operate in its most linear operating region. Figure 48 shows the differential gain curve. The ISL59530 is a single supply 5V design with its most linear region between 0.1 and 2V. This range is fine for most video signals whose nominal signal amplitude is 1V. The most negative input level (the sync tip for composite video) should be maintained at 0.3V or above for best operation.
Bandwidth Considerations
Wide frequency response (high bandwidth) in a video system means better video resolution. Four sets of frequency response curves are shown in Figure 47. Depending on the switch configurations, and the routing (the path from the input to the output), bandwidth can vary between 100MHz and 350MHz. A short discussion of the trade-offs -- including matrix configuration, output buffer gain selection, channel selection, and loading -- follows.
2
Mux, Av = 2
0 Normalized Gain [dB] -2 -4 -6 -8 -10
Broadcast, Av = 2 Broadcast, Av = 1
Mux, Av = 1
1
10 100 Frequency [MHz]
1000
FIGURE 48. DIFFERENTIAL GAIN RESPONSE
FIGURE 47. FREQUENCY RESPONSE FOR VARIOUS MODES
In multiplexer mode, one input typically drives one output channel, while in broadcast mode, one input drives all 16 outputs. As the number of outputs driven increases, the parasitic loading on that input increases. Broadcast Mode is the worst-case, where the capacitance of all 16 channels loads one input, reducing the overall bandwidth. In addition, due to internal device compensation, an output buffer gain of x2 has higher bandwidth than a gain of x1. Therefore, the highest bandwidth configuration is multiplexer mode (with each input mapped to only one output) and an output buffer gain of x2. The relative locations of the input and output channels also have significant impact on the device bandwidth (due to the layout of the ISL59530 silicon). When the input and output channels are further away, there are additional parasitics as a result of the additional routing, resulting in lower bandwidth. The bandwidth does not change significantly with resistive loading as shown in the typical performance curves. However several of the curves demonstrate that frequency response is sensitive to capacitance loading. This is most significant when laying out the PCB. If the PCB trace length between the output of the crosspoint switch and the backtermination resistor is not minimized, the additional parasitic capacitance will result in some peaking and eventually a reduction in overall bandwidth.
In a DC-coupled application, it is the system designer's responsibility to ensure that the video signal is always in the optimum range. When AC coupling, the ISL59530's DC restore function automatically adjusts the DC level so that the most negative portion of the video is always equal to VREF. A discussion of the benefits of the DC-restored system begins by understanding the block diagram of a typical DCrestore circuit (Figure 49). It consists of 4 sections: an AC coupling (DC blocking) capacitor at the input, an opamp, a FET switch, and a current source. In the absence of an input signal, RTERM pulls the input node to ground. The 2A current source slowly drains the input capacitor of charge, slowly lowering VOUT. However when VOUT goes below VREF, Q1 turns on, sourcing current into the capacitor until VOUT is equal to VREF, at which point Q1 will turn off. So with no VIN signal, the voltage at the noninverting input of the opamp will settle to approximately VREF, with Q1 sourcing the same 2A as the current source.
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0.086F. Figure 50 shows the result of CIN = 0.1F delivering acceptable droop and CIN = 0.001F producing excessive droop
VS VREF VIN RTERM CIN
+
Q1 VOUT 2uA
When the clamp function is disabled in the CONTROL register (Clamp = 0) to allow DC-coupled operation, the ICLAMP current sinks/sources are disabled and the input passes through the DC Restore block unaffected. In this application VREF may be tied to GND.
Overlay Operation
The ISL59530 features an overlay feature, that allows an external video signal or DC level to be inserted in place of that output channel's video. When the OVERN signal is taken high, the output signal on the OUTN pin is replaced with the signal on the VOVERN pin. There are several ways the overlay feature can be used. Toggling the OVERN signal at the frame rate or slower will replace the video frame(s) on the OUTN pin with the video supplied on the VOVERN pin. Another option (for OSD displays, for example), is to put a DC level on the VOVERN line and toggle the OVERN signal at the pixel rate to create a monocolor image "overlaid" on channel N's output signal. Finally, by enabling the OVERN signal for some portion of each line over a certain amount of lines, a picture-in-picture function can be constructed. It's important to note that the overlay inputs do not have the DC Restore function previously described - the overlay signal is DC coupled into the output. It is the system designer's responsibility to ensure that the video levels are in the ISL59530's linear region and matching the output channel's offset and amplitude. One easy way to do this is to run the video to be overlaid through one of the ISL59530's unused channels and then into the VOVERN input. The OVERN pins all have weak pulldowns, so if they are unused, they can either be left unconnected or tied to GND.
FIGURE 49. DC RESTORE BLOCK DIAGRAM
When a video signal is applied to VIN, the most negative signal will be the sync tip. If the sync tip goes below VREF, Q1 will turn on and quickly source enough current into CIN so that the sync tip is forced to be equal to VREF. After the sync tip, the video jumps up by 300mV or more, so VOUT becomes >> VREF, so Q1 will not turn on for the rest of the video line. However the 2A current source continues to slowly discharge CIN, so that by the end of the video line, the next sync tip will again be slightly below VREF, forcing Q1 to source some current into C1 to make VOUT = VREF during the sync tip. This is how the video is "DC-restored" after being AC coupled into the ISL59530. The sync tip voltage will be equal to VREF, on the right side of CIN, regardless of the DC level of the video on the left side of CIN. Due to various sources of offset in the actual clamp function, the actual sync tip level is typically about 75mV higher than VREF (for VREF = 0.5V). .
Power Dissipation and Thermal Resistance
With a large number of switches, it is possible to exceed the 150C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the crosspoint switch in a safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA
FIGURE 50. DC RESTORE VIDEO WAVEFORMS
It is important to choose the correct value for CIN. Too small a value will generate too much droop, and the image will be visibly darker on the right than on the left. A CIN value that is too large may cause the clamp to fail to converge. The droop rate (dV/dt) is iPULLDOWN/CIN volts/second. In general, the droop voltage should be limited to <1 IRE over a period of one line of video; so for 1 IRE = 7mV, IB = 10A maximum, and an NTSC waveform we will set CIN > 10A*60s/7mV = 20
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Where: * TJMAX = Maximum junction temperature = 125C * TAMAX = Maximum ambient temperature = 85C * JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or:
n
PD MAX = V S x I SMAX +
i=1
( VS - VOUTi ) x ----------------R Li
V OUTi
Where: * VS = Supply voltage = 5V * ISMAX = Maximum quiescent supply current = 360mA * VOUT = Maximum output voltage of the application = 2V * RLOAD = Load resistance tied to ground = 150 * n = 1 to 16 channels
n
PD MAX = V S x I SMAX +
i=1
( VS - VOUTi ) x ----------------- = R Li
V OUTi
2.44W
The required JA to dissipate 2.44W is:
T JMAX - T AMAX JA = -------------------------------------------- = 16.4 ( C/W ) PD MAX
Table 8 shows JA thermal resistance results with a Wakefield heatsink and without heatsink and various airflow. At the thermal resistance equation shows, the required thermal resistance depends on the maximum ambient temperature.
TABLE 8. JA THERMAL RESISTANCE [C/W] Airflow [LFM] No Heatsink Wakefield 658-25AB Heatsink 0 18 16.0 250 14.3 7.0 500 13.0 6.0 750 12.6 4.7
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 21
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ISL59530
356 Ld PBGA Package
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